Small is beautiful...
The DμART is one of the tiniest UART IP Cores available on the market.
DμART bridge to APB, AHB, AXI bus, it is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read a complete status of the UART at any time during the functional operation. The reported status information includes a type and condition of the transfer operations performed by the UART, as well as any error conditions (overrun, framing). The DμART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing 16 × clock for driving internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The DμART has a processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communication link. The core is perfect for applications where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices.
Watch the DμART presentation on DCD’s You Tube:
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Majority Voting Logic
- Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data
- In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data
- Independently controlled transmit, receive, line status, and data set interrupts
- 16 bit programmable baud generator
- False start bit detection
- Line break generation and detection. Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Overrun, framing error detection
- Full prioritized interrupt system controls
- Technology independent HDL Source Code
- Fully synthesizable static design with no internal tri-state buffers
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus