DQSPI bridge to APB, AHB, AXI bus, it is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, the IP Core supports all 8, 16, 32 bit processors available on the market. The DQSPI is a fully configurable SPI master/slave device, which allows you to configure polarity and phase of serial clock signal SCK. It enables the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of information on four serial data lines. In the Single SPI mode, data is simultaneously transmitted and received, while in DUAL and QUAD SPI modes, data is shifted in or out respectively on two and four  data lines at once. Additionally, transfer speed can be doubled by using the DDR protocol (Double Data Rate) – this feature allows the DQSPI to transfer/receive data on both falling and rising edges of SCK. The DDR together with QUAD SPI transfer allow 8 bits of data to be sent/received within a single SCK clock cycle. This makes the DQSPI perfect for systems, where performance is essential, or where the code can be moved from non-volatile memory to fast RAM, or for systems where device size and cost are the key, or where the program code can be executed directly from non-volatile memory, using an approach known as Execute-in-Place. DCD’s IP Core is a technology independent design that can be implemented in variety of process technologies. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows selecting clock polarity, phase and four fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drives selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and addresses SPI slave device to exchange serially shifted data. Error‐detection logic is included, to support interprocessor communications. A write‐collision detector indicates when an attempt is made to write data to the serial shift register, while the transfer is in progress. A multiple-master mode‐fault detector disables DQSPI output drivers automatically, if more than one SPI device simultaneously attempts to become a bus master. The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow the DQSPI to interface to higher performance DMA units which can interleave their transfers between CPU cycles or execute multiple byte transfers. The DQSPI is fully customizable – it is delivered in the exact configuration to meet your requirements.

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Key features

  • Operates with 8, 16 and 32 bit CPUs
  • Full duplex synchronous serial data transfer
  • DMA support
  • Support for 32, 16 and 8 bit systems
  • Support for various system Bus Standards
  • Single, Dual and Quad SPI transfer
  • DDR support (Double Data Rate)
  • Multimaster system supported
  • Optional FIFO size extension (128, 256, 512B)
  • Up to 7 SPI slaves can be addressed (more Slave Select Outputs can be added upon request)
    • Software Slave Select Output – SSO ‐ selection
    • Automatic Slave Select outputs assertion during each byte transfer
  • System error detection
  • Interrupt generation
  • Various Bit rates supported
  • Bit rate in fast SPI Mode ½ CLK
  • Four transfer formats
  • Simple SPU and DMA interface
  • Fully synthesizable, static synchronous de-sign with no internal tri‐states
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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