Multiprotocol Enhanced Serial Communication Controller
multiprotocol combo: HDLC, UART, SPI... with bigger FIFO and...
DMESCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors.
DMESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The DMESCC also has facilities for modem control in both channels.
The user can configure DMESCC to handle all asynchronous formats regardless of data size, number of stop bits, or parity requirements. Control is done through the number of control and status registers for each channel separately. Within each operating mode, the DMESCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.
The ultimate functionality of DMESCC denotes its usability:
- as a data communications device, DMESCC transmits and receives data in a wide variety of data communication protocols.
- as a microprocessor peripheral, it offers valuable features such as vectored interrupts, polling, and simple handshake capability.
The DMESCC provides two independent full-duplex channels, programmable for use in any standard asynchronous or synchronous data communication protocol. In Asynchronous mode transmission and reception can be accomplished independently on each channel with 5 to 8 bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection logic interrupts the CPU.
All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Dual-Channel: A, B
- Configuration capability
- Asynchronous mode:
- Asynchronous (x16, x32, or x64 clock
- Isochronous (x1 clock)
- Character-Oriented mode:
- External Synchronous
- Bit-Oriented mode:
- ◊ SDLC/HDLC
- ◊ SDLC/HDLC Loop
- Complete status reporting capabilities
- Receiver data FIFO and Error FIFO
- SDLC Frame FIFO
- Transmitter FIFO
- Data encoder\decoder:
- NRZ, NRZI
- FM0, FM1
- Manchester (require external logic)
- Line break generation and detection
- Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Auto Echo
- Break, parity, overrun, framing error simulation
- Fully synchronous design with no internal tri-state buffers
- Synchronous Byte (Bisync) features
- 5 to 8 Bit characters
- Programmable Sync character
- Transparent text mode operation
- Automatic Sync insertion during Idle
- Hardware CRC generation and detection
- CRC-16 or CRC-CCITT polynomials
- Asynchronous Features
- 5-8 Bits per character
- 1, 1,5, and 2 stop bits
- Break generation and detection
- Parity, overrun, and framing error detection
- Even, Odd or no parity
- Modem controls and indicators
- CTS and DCD lines, usable for modem control or user-defined input
- DTR and RTS usable for modem control or user-defined output
- Synchronous SDLC features
- 1-8 Bits character (transmitter)
- 5-8 Bits receiver character
- Hardware address recognition
- Automatic zero insertion and deletion
- I-Field residue handling
- Automatic flag insertion between messages
- Hardware CRC generation and reception
- Interrupt system features
- Channel functions and timers internally prioritized
- Channel functions and timers generate unique interrupt mode
- Prioritized Daisy-chain.
- LOOPBACK test mode
DHDLC bridge to APB, AHB, and AXI bus, provides versatile support for a widely used HDLC transmission protocol. It...
+ Receiver and transmitter interfaces
+ Supports CRC16 and CRC32
+ Bit stuffing and unstuffing
DμART bridge to APB, AHB, AXI bus, it is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It...
Majority Voting Logic
Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data
In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data