DI2S bridge to APB, AHB, AXI bus, it is a universal solution which provides an interface between a microprocessor and I2S, left/right justified modes, PCM, TDM audio protocol codec. Thanks to flexible configuration it can work as a receiver, transmitter in master or slave mode, with configurable channel length or sample size. Additionally, number of audio blocks can be adjusted according to specific project needs.


All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.

  • Altera / Intel,
  • Xilinx / AMD,
  • Lattice,
  • Microsemi / Microchip,
    and others.

  • TSMC
  • UMC
  • SK Hynix
    and others.


Key features

  • Configurable number of independent audio modules with their respective FIFO
  • Configurable TX/RX mode of each audio module
  • Configurable master/slave mode support of each audio module
  • Flexible I2S, LSB/MSB (right/left) justified, DSP, TDM modes support
  • Configurable sample size (8, 10, 16, 20, 24, 32 bit)
  • Configurable number of samples per frame (1 to 16)
  • Configurable FIFO depth
  • Flexible FIFO threshold interrupt control
  • FIFO Underrun/overrun interrupt
  • Inter modules clock synchronization
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus