DF6811E

The DF6811 is an advanced 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities. The IP Core is binary-compatible with industry standard Motorola 68HC11 8-bit microcontroller. It has an improved FAST architecture which is approximately 4 times faster compared to the original implementation. In the standard configuration the core has major peripheral functions integrated on-chip. It can be provided in configurations that match the following specs:

• 68HC11A
• 68HC11D
• 68HC11E

There are two serial interfaces: an asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring circuitry is included on-chip to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available to save additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications. The DF6811E Microcontroller Core can be equipped with ADC Controller, allowing use of external ADC Controller with a standard ADC software. The ADC Controller makes external ADC’s visible as internal ADC’s in original 68HC11E Microcontrollers. The DF6811E is fully customizable – delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The DF6811E comes with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each DCD’s DF68XX Core has a built-in support for proprietary Hardware Debug System called DoCD™ – a real-time hardware debugger providing debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ allows non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

DESIGN FEATURES:

All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• FAST architecture, 4 times faster than the original implementation
• Software compatible with industry standard 68HC11
• 10 times faster multiplication
• 16 times faster division
• 256 bytes of remapped System Function Registers space (SFRs)
• De-multiplexed Address/Data Bus for easy memory connection
• The core can also be used without I/O wrapper, so each peripheral functions pins will be separated from I/O ports lines.
• Two power saving modes: STOP, WAIT
• Ready pin allows the Core to operate with slow program and data memories.
• Fully synthesizable
• Static synchronous design
• No internal reset generator or gated clock
• Positive edge clocking and no internal tri-states
• Scan test ready
• 1 GHz of virtual clock frequency compared to the original implementation
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available