The DAES - cryptographic co-processor which provides FIPS 197 compliant Advanced Encryption Standard acceleration.


DAES bridge to APB, AHB, AXI bus, it is a cryptographic co-processor which implements Rijndael encryption algorithm compliant with FIPS 197 Advanced Encryption Standard. AES is a widely deployed block cipher in security solutions from IoT devices to cloud servers. Its implementation in hardware brings significant benefits on fields of security and performance over software one.


All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.

  • Altera / Intel,
  • Xilinx / AMD,
  • Lattice,
  • Microsemi / Microchip,
    and others.

  • TSMC
  • UMC
  • SK Hynix
    and others.

DCD’s cryptographic system has been awarded as the Most Innovative IP Core of the Year during IP SoC China

Download full specification

Key features

  • Support for 128 and 256 key bit length
  • Support for ECB, CBC, CFB, OFB, CTR block cipher modes
  • Internal key expansion module
  • Flexible data read/write modes
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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