D8530

D8530 bridge to APB, AHB, AXI bus, it is a dual-channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, designed for use with 8 and 16-bit microprocessors. It works as a serial-to-parallel, parallel-to-serial converter/controller and can be software-configured to satisfy a wide range of serial communications applications. The device contains a variety of new, sophisticated internal functions, including on-chip baud rate generators. The D8530 handles asynchronous formats, synchronous byte-oriented protocols (such as IBM® Bisync), and synchronous bit-oriented protocols, like HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (telecommunication, LAN, etc.). It can also generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The D8530 supports modem control in both channels – in applications where these controls are not needed, modem controls can be used for general-purpose I/O. You can configure the IP Core to handle all synchronous formats, regardless of data size, stop bits, or parity requirements. The D8530 is controlled through access to 14 Write registers and 7 Read registers per channel (the number of the registers varies depending on the version). Within each operating mode the D8530 allows protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others. 

   

• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with Z85C30
• Dual Channel: A, B
• Configuration capability
• Asynchronous mode:
  • Asynchronous (x16, x32, or x64 clock
  • Isochronous (x1 clock)
• Character-Oriented mode:
  • Monosynchronous
  • Bisynchronous
  • External Synchronous
• Bit-Oriented mode:
  • SDLC/HDLC
  • SDLC/HDLC Loop
• Complete status reporting capabilities
• Receiver data FIFO and Error FIFO
• SDLC Frame FIFO
• Data encoder\decoder:
  • NRZ, NRZI
  • FM0, FM1
  • Manchester (require external logic)
• Line break generation and detection
• Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Auto Echo
  • Break, parity, overrun, framing error simulation
• Fully synchronous design with no internal tristate buffers
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus