D8255

The D8255 is a programmable I/O device designed for use with all Intel CPUs. What’s significant, it also supports most other microprocessors. Our innovative IP core provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation:

• MODE 0 – Basic Input/Output. This functional configuration provides simple input and output operations for each of the three ports. No „handshaking” is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions:
  ◦ Two 8-bit ports and two 4-bit ports,
  ◦ Any port can be input or output,
  ◦ 16 different Input/Output configurations are possible in this Mode.
• MODE 1 – Strobed Input/Output. This functional configuration provides means for transferring I/O data to or from a specified port in conjunction with strobes or „handshaking” signals. In mode 1, Port A and Port B use the lines on Port C, to generate or accept these „handshaking” signals. Mode 1 Basic functional Definitions:
  ◦ Two Groups (Group A and Group B).
  ◦ Each group contains one 8-bit data port and one 4-bit control/data port.
  ◦ The 8-bit data port can be either input or output Both inputs and outputs are latched.
  ◦ The 4-bit port is used for control and status of the 8-bit data port.
• MODE 2 – Strobed Bidirectional Bus I/O. This functional configuration provides means for communicating with a peripheral device or structure on a single 8-bit bus, both for transmitting and receiving data (bidirectional bus I/O). „Handshaking” signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions:
  ◦ Used in Group A only.
  ◦ One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).
  ◦ The 5-bit control port (Port C) is used for control and status of the 8-bit, bi-directional bus port (Port A).

The functional configuration of the D8255 is programmed by the system software so that normally no external logic is needed to interface peripheral devices or structures.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others. 

   

• TSMC
• UMC
• SK Hynix
  and others.

• Compatible with industry standard 8255
• 24 I/O lines individually programmed
  in 2 groups of 12:
  • Group A – Port A and upper half of Port C
  • Group B – Port B and lower half of Port C
• 3 major modes of operation
  • Mode 0 – Basic input/output
  • Mode 1 – Strobed Input/output
  • Mode 2 – Bi-directional Bus
• Control Word Read-Back Capability
• Direct Bit Set/Reset Capability
• Interrupt control functions
• No internal three states busses
• Fully synthesizable, technology independent source code.