8-bit Microcontroller IP – legacy architecture – raplacement of 68HC11K MCU’s
The D68HC11K is synthesisable soft IP Core Microcontroller, fully compatible with the industry standard. It can be used as a direct replacement for the following Motorola MC68HC11K microcontrollers:
In a standard configuration of the core, major peripheral functions are integrated on-chip. An asynchronous serial communication interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Self-monitoring on-chip circuitry is included, to protect the D68HC11K against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available, to preserve additional power. These modes make the D68HC11K IP Core especially attractive for automotive and battery-driven applications. The D68HC11K Microcontroller Core can be equipped with an ADC Controller, allowing use of external ADC Controller with standard ADC software. The ADC Controller makes external ADC’s visible as internal ADC’s in original 68HC11K Microcontrollers. The D68HC11K is fully customizable – it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The D68HC11K comes with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each DCD’s DF68XX and D68HC11X Core has a built-in support for DCD’s Hardware Debug System called DoCD™. It is a real-time hardware debugger which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Cycle compatible with original implementation
- Software compatible with 68HC11K industry standard
- I/O Wrapper, making it pin-compatible core
- SFR registers remapped to any 4KB memory page
- Two power saving modes: STOP, WAIT
- Fully synthesizable
- Static synchronous design
- No internal tri-states
- Scan test ready
- USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
|IP Core||Architecture type||Memory space||DoCD||UART (SCI)||SPI M/S||IO Ports||Watchdog Timer||Timer||Compare / Capture||Pulse accumulator||READY pin||Chip Selects||Gatecount|
Power of Innovation is our primary target. That’s why our R&D focuses on every IP Core detail. As a result of that concern, some unique solutions were born. One of them is the 68XX on-Chip Debugger (DoCD™), which is a complete debugging system, dedicated for all 68XX Cores offered by DCD.Read more
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