D68HC11F

The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. In the standard configuration of the core, major peripheral functions are integrated on-chip. An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring on-chip circuitry is included, to protect the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available, to preserve additional power. These modes make the D68HC11F IP Core especially attractive for automotive and battery-driven applications. The D68HC11F Microcontroller Core can be equipped with an ADC Controller, allowing the use of an external ADC Controller with standard ADC software. The ADC Controller makes external ADCs visible as internal ADCs in original 68HC11F1 Microcontrollers. The Core is fully customizable – it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The D68HC11F comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s D68HC11F Core has built-in support for DCD’s Hardware Debug System called DoCD™ – a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others. 
• TSMC
• UMC
• SK Hynix
  and others.

• Cycle compatible with original implementation
• Software compatible with 68HC11 industry standard
• I/O Wrapper making it pin-compatible core
• SFR registers remapped to any 4KB memory page
• Two power saving modes: STOP, WAIT
• Fully synthesizable
• Static synchronous design
• No internal tri-states
• Scan test ready
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available