D68000-CPU32
16/32-bit Microprocessor CPU32 (68020)
Description
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000’s CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and 24-bit address data bus. It is code compatible with the 68000’s CPU32 (version of MC68020). The D68000-CPU32 has an improved instructions set, which allows program execution with higher performance than the standard 68000 core. It contains a built-in DoCD-BDM on-chip debugger interface. The D68000-CPU32 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
DESIGN FEATURES:
All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.
- Altera / Intel,
- Xilinx / AMD,
- Lattice,
- Microsemi / Microchip,
and others. - TSMC
- UMC
- SK Hynix
and others.
Key features
- Software compatible with industry standard 68000’s CPU32 (68020)
- DoCD-BDM on-chip debugger as in CPU32
- VBR register
- Bus cycle timings identical to 68000
- 32-bit data and address registers
- 16 addressing modes:
- Direct:
- Data register direct – Dn
- Address register direct – An
- Indirect:
- Register indirect – (An)
- Post-increment register indirect – (An+)
- Pre-decrement register indirect – (-An)
- Register indirect with offset – (d16,An)
- Indexed register indir. with offset – (d8,An,Xn)
- Indexed register indir. with offset and base displacement – (bd,An,Xn)
- PC relative:
- with offset(d16,PC); with index and offset – (d8,PC,Xn)
- with index offset and base displacement – (bd,PC,Xn)
- Absolute data:
- Absolute short (.W)
- Absolute long (.L)
- Immediate data:
- Immediate – #data
- Quick immediate – #n
- Implied
- Direct:
- 5 data types supported:
- bits, BCD
- bytes, words and long words
- Arithmetic Logic Unit includes:
- 8,16,32-bit arithmetic & logical operations
- 16×16, 32×32 bit signed and unsigned multiplication
- 32/16, 32/32, 64/32 bit signed and unsigned division
- Boolean operations
- Interrupt controller:
- 7 priority levels interrupt controller
- Unlimited number of virtual interrupt sources
- Vectored and auto-vectored modes
- Format $0, $2, $C exceptions support as in CPU32
- Memory interface includes:
- Up to 16 MB of address space
- 16-bit data bus
- Asynchronous bus control
- M6800 family synchronous interface
- 3- and 2- wire bus arbitration
- Supervisor and user modes
- Fully synthesizable, static synchronous design with no internal tri-states
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