D2692 bridge to APB, AHB, AXI bus, it is a dual channel UART Core, software compatible with SC26C92, SCC2692 and SCN2681, with added features and deeper FIFOs. It contains: 8 character receiver, 8 character transmit FIFOs, watchdog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts. The D26C92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system, plus, it provides a modem and DMA interface. An operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to program operating speed of the receiver and transmitter independently, makes the UART particularly attractive for dual-speed channel applications, such as clustered terminal systems.

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Key features

  • Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
  • Configuration capability
  • Dual full-duplex independent asynchronous receiver/transmitters
  • 8 character FIFOs for each receiver and transmitter
  • Programmable data format:
    • 5 to 8 data bits plus parity
    • Odd, even, no parity or force parity
    • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
  • 16-bit programmable Counter/Timer
  • Programmable baud rate for each receiver and transmitter selectable from:
    • 27 fixed rate
    • Other baud rates – at 16X
    • Programmable user-defined rates derived from a programmable counter/timer
    • External 1X or 16X clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Programmable channel mode:
    • Normal (full-duplex)
    • Automatic echo
    • Local loopback
    • Remote loopback
    • Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
  • Multi-function 7-bit input port:
    • Can serve as clock, modem, or control inputs
    • Change of state detection on four inputs
  • Multi-function 8-bit output port:
    • Individual bit set/reset capability
    • Outputs can be programmed to be status/interrupt signals
    • FIFO states for DMA and modem interface
  • Versatile interrupt system:
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
    • Each FIFO can be programmed for four different interrupt levels
    • Watch dog timer for each receiver
  • Automatic wake-up mode for multidrop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • Power down mode
  • Receiver timeout mode
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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