CAN FD Bus Controller
The automotive IPs are developed as ISO26262-10 Safety Element out of Context (ISO26262 soft IP SEooC, ASIL-B ready design)
The DCAN FD bridge emerges as a robust, standalone controller seamlessly interfacing with APB, AHB, and AXI buses. Tailored for the Controller Area Network (CAN) in automotive and industrial domains, it strictly adheres to ISO 11898-1:2015 standards. This versatile controller supports:
- Bosch CAN 2.0B specification (2.0B Active)
- and CAN FD (flexible data-rate).
Distinguished by cutting-edge error detection functions and fault confinement mechanisms, the DCAN FD is a linchpin in automotive and industrial communications. For those prioritizing security and safety, DCD-SEMI presents a superior IP Core meeting the highest quality standards.
Breaking through traditional CAN limitations, this protocol facilitates faster data transmission exceeding 1 Mbit/s and extends the payload to an impressive 64 bytes, no longer confined to 8 bytes. Enjoy increased bit rates when a single node transmits, eliminating the need for synchronization with other nodes. The core boasts a user-friendly CPU interface (configurable data width of 8/16/32 bits) with a flexible addressing scheme (small or big-endian). Hardware message filtering (32 filters) and a 128-byte receive FIFO ensure seamless, low-CPU-load message reception. As an HDL source code, the DCAN FD seamlessly integrates into FPGA and ASIC technologies.
Choose between the Basic and Safety-Enhanced versions of the IP core. The Safety-Enhanced variant, developed as an ISO26262-10 Safety Element out of Context, can be fortified with essential safety mechanisms. DCD-SEMI provides exhaustive safety documentation, including ISO26262 soft IP SEooC work products, a comprehensive Failure Modes Effects and Detection Analysis (FMEDA) with integration instructions, and system-level safety analysis. Third-party audits authenticate all safety-related work products.
The safety analysis affirms compliance with stringent safety metrics, with both IPs achieving Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI offers a detailed FMEDA analysis with instructions, facilitating seamless integration into the customer’s system and robust system-level safety analysis.
This ASIL-B ready design proves ideal for integration into Automotive Safety Systems at the ASIL-B level, with the flexibility for DCD-SEMI to deliver higher ASIL-level ready IP. For more information and insight into optional features, please reach out to our dedicated support team. Elevate your automotive and industrial communication capabilities with the unparalleled performance of the DCAN FD bridge.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Designed in accordance to ISO 11898-1:2015
- Supports CAN 2.0B and CAN FD frames
- Supports up to 64 bytes data frames
- Flexible data-rates supported
- Supports emotas CANopen FD stack
- 8/16/32-bit CPU slave interface with small or big endianness
- Simple interface allows easy connection to CPU
- Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
- Data rate up to 8 Mbps
- Hardware message filtering (dual/single filter) – up to 32 filters
- Configurable size of RX/TX memories
- Overload frame is generated on FIFO overflow
- Normal & Listen Only Mode
- Transceiver Delay Compensation up to three data bit long
- Single Shot transmission
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Fully synthesizable
- Static synchronous design with positive edge clocking and synchronous reset
- No internal tri-states
- Scan test ready
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Lite Bus
- Altera Avalon Bus
- Xilinx OPB Bus
DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That's why...
+ Conforms to LIN 1.2, 2.1, 2.2A spec
+ Automatic LIN Header handling
+ Automatic Re-synchronization
DμART bridge to APB, AHB, AXI bus, it is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It...
Majority Voting Logic
Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data
In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data