CAN FD Full Bus Controller

Introducing the CAN FD FULL IP Core – your gateway to bridging the gap between CAN FD and CAN XL. Aptly named “CPU friendly,” this innovative solution efficiently eases the burden on your processor through configurable registers and a host of additional innovations.

DCD’s CAN FD FULL IP Core stands as a dynamic and flexible solution, seamlessly integrating Controller Area Network (CAN) functionality into diverse systems. Whether implemented independently, as part of an ASIC, or on an FPGA, this IP module follows the ISO11898-1:2015 standard, ensuring smooth communication in alignment with industry protocols.

Supporting both Classical CAN and CAN FD, this module, while requiring external transceiver hardware for a physical connection to the CAN bus, stands out with its utilization of a single or dual-ported Message RAM located outside the module. This storage medium is intricately connected to the CAN FD Full through the Generic Master Interface, streamlining and enhancing message handling efficiency.

Connecting your host CPU to the CAN FULL IP Core module is a breeze with the 32-bit Generic Interface, facilitating seamless integration and optimized data exchange. The Core supports popular interface wrappers such as AMBA – APB / AHB / AXI Lite Bus, Altera Avalon Bus, and Xilinx OPB Bus.

Choose between two versions of the IP core – Basic and Safety-Enhanced. Developed as an ISO26262-10 Safety Element out of Context, the Safety-Enhanced variant offers optional enhancements with necessary safety mechanisms. It also provides detailed safety documentation, including all ISO26262 soft IP SEooC required work products. This encompasses a comprehensive Failure Modes Effects and Detection Analysis (FMEDA) with step-by-step instructions, ensuring smooth integration into your system and facilitating system-level safety analysis. All safety-related work products undergo scrutiny through third-party, independent audits.

The safety analysis affirms that both IPs meet stringent safety metrics, achieving the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD delivers a thorough FMEDA analysis with instructions, supporting your integration process and system-level safety analysis.

This ASIL-B ready design is tailor-made for integration into Automotive Safety Systems at the ASIL-B level. However, for those seeking even higher ASIL-level readiness, DCD offers optional features and enhancements. For further details and information on these optional features, reach out to our dedicated support team. Elevate your communication capabilities with the CAN FD FULL IP Core – where innovation meets efficiency in the world of automotive safety.

CAN FuSa white papers

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Designed in accordance to ISO 11898-1:2015
• Supports CAN 2.0B and CAN FD frames
• Supports up to 64 bytes data frames
• Flexible data-rates supported
• Supports emotas CANopen FD stack
• 8/16/32-bit CPU slave interface with small or big endianness
• Simple interface allows easy connection to CPU
• Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
• Data rate up to 8 Mbps
• Hardware message filtering (dual/single filter) – up to 32 filters
• 128 byte receive FIFO and transmit buffer
• Overload frame is generated on FIFO overflow
• Normal & Listen Only Mode
• Transceiver Delay Compensation up to three data bit long
• Single Shot transmission
• Ability to abort transmission
• Readable error counters
• Last Error Code
• Fully synthesizable
• Static synchronous design with positive edge clocking and synchronous reset
• No internal tri-states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Lite Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus