CAN 2.0 Bus Controller with Functional Safety
The automotive IPs are developed as ISO26262-10 Safety Element out of Context (ISO26262 soft IP SEooC, ASIL-B ready design)
DCAN 2.0 bridge to APB, AHB, AXI bus, it is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It was designed in accordance with ISO 11898-1:2015 and conforms to:
- Bosch CAN 2.0B specification (2.0B Active) and
Sophisticated error detection functions (which increase communication reliability) and unique fault confinement (which guarantees network-wide data consistency) has decided about CAN’s popularity. Because of its fundamental role in all aspects of security and safety, trustworthy implementations are crucial. That’s why DCD-SEMI developed a unique IP Core, which delimits the highest quality standards. The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the payload (data field) is up to 64 bytes long and limited to 8 bytes. When only one node is transmitting, the bit rate can be increased, because no nodes need to be synchronized. Of course, before transmitting the ACK slot bit, the nodes need to be re-synchronized. The core has a simple CPU interface (8/16/32 bit configurable data width), with a small or big-endian addressing scheme. Hardware message filtering (32 filters) and 128 bytes receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN is provided as HDL source code, allowing target use in FPGA and ASIC technologies.
The IP core is available in two versions – Basic and Safety-Enhanced.
This sophisticated solution has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.
The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instructions to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.
This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD-SEMI may optionally deliver higher ASIL-level ready IP. For further information and the optional features please contact our support.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Designed in accordance to ISO 11898-1:2015
- Supports CAN 2.0B and CAN FD frames
- Supports up to 64 bytes data frames
- Flexible data-rates supported
- Supports emotas CANopen FD stack
- 8/16/32-bit CPU slave interface with small or big endianness
- Simple interface allows easy connection to CPU
- Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
- Data rate up to 8 Mbps
- Hardware message filtering (dual/single filter) – up to 32 filters
- Configurable size of RX/TX memories
- Overload frame is generated on FIFO overflow
- Normal & Listen Only Mode
- Transceiver Delay Compensation up to three data bit long
- Single Shot transmission
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Fully synthesizable
- Static synchronous design with positive edge clocking and synchronous reset
- No internal tri-states
- Scan test ready
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Lite Bus
- Altera Avalon Bus
- Xilinx OPB Bus
DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That's why...
+ Conforms to LIN 1.2, 2.1, 2.2A spec
+ Automatic LIN Header handling
+ Automatic Re-synchronization
DμART bridge to APB, AHB, AXI bus, it is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It...
Majority Voting Logic
Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data
In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data