D68000 IP Core with Linux, MAC & debugger
DCD-SEMI, IP Core and SoC design laboratories from Poland have introduced the newest version of the Motorola’s 68000 16/32-bit microprocessor. D68000 is the industry’s low cost 32-bit MCU, offering not only a low cost entry point but also effective performance. Improved architec-ture enables this IP Core to run with uCLinux, so it can be  easily used as HTTP server or FTP client.

The D68000 is 100% compatible with original Motorola’s 68000 and as a proof, just to mention, that a test run on classic Amiga 500+ computer showed clearly that DCD’s CPU can be 1:1 replacement for original chip. But classic computers are not the target destination for the product, cause improved architecture, creates new possibilities. D68000 runs with uCLinux Operating System, which makes this IP Core interesting solution for embedded servers, certified to be used only with m68k processors. The BOA application is used as HTTP server and effective communication could be established through FTP protocol. uCLinux is a MMU‐less derivative of Linux Operating System adopted for embedded solutions. It provides all of the Linux benefits including superior stability, Common Linux Kernel API, multitasking, full featured TCP/IP networking, Virtual File System and reduces the amount of memory needed by its kernel and running applications [it utilizes just 400kB].
To make implementation process even easier DCD’s solution is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.  – We have built special testing platform to run D68000 with uCLinux Operating System – explains Jacek Hanke, President of DCD-SEMI – And to make this IP Core more user friendly, it’s being equipped with DoCD-BDM hardware debugger.
New IP Core from DCD is a technology independent solution, which enables any engineer to imple-ment it in either Altera, Asic, Lattice or Xilinx technology. Of course D68000 is binary-compatible with m68k family of microprocessors, more over – DCD’s D68000 has a 16-bit data bus and a 24-bit address data bus. Its code is compatible with the MC68008, upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. The difference lies in improved instructions set, which allows to execute a program with a higher performance, than the standard 68000 core can offer. MULS, MULU take just 28 clock periods, the same as DIVS, DIVU. Optimized shifts and rotations, combined with shorter effective address calculation time and removed idle cycles make this IP Core much more power efficient.
To complement the D68000 offer, it’s being developed with DoCD-BDM hardware debugger, which provides debugging capability not only for the IP Core, but for the whole SoC system. DCD’s debug-ger is 100% compatible with BDM debug interfaces, working smoothly with its interfaces/cables: Public Domain cable, Macraigor Wiggler and P&E BDM cable. DoCD’s also fully supported by stand-ard debugging tools like GNU GD8 debugger, Cosmic ZAP debugger and Tasking debugger.

Automotive is the key: DCAN
DCD-SEMI, as a leading IP Core provider and System-on-Chip (SoC) design house, has been invited for a conference “Know-how transfer in automotive”. The conference was held during international Fair of Automation and Robotization in Industry at Expo Silesia, Poland.

Bytom, Poland November 17th, 2011. DCD-SEMI as a proprietary automotive IP Core provider participated in fair show and the international conference devoted to know-how transfer. Poland and Silesia Region particularly is one of the leading country regarding to automotive business in Europe. Thanks to the main European FIAT fab and OPEL (General Motors) factory which manufacture their newest car models, growth rate is positive, even though economy crisis. Strict cooperation with concerns propels also proprietary solutions providers. – We noticed that safety & power safe technologies are becoming one of the most significant ones, not only in automotive – says Tomasz Krzyzak, vice-president at DCD-SEMI – that’s why not only our CPU solutions but also “automotive” interfaces CAN or LIN are equipped with enhanced control and power safe solutions.
Like for example CAN is a keyword connecting the world of electronics with the world of automotive. Because of its fundamental role in all aspects of security and safety, trustworthy implementations are crucial. That’s why DCD-SEMI developed unique IP Core, which delimits the highest quality standards. The DCAN is a standalone controller for the Controller Area Network (CAN), which is common used in automotive and industrial applications. What’s the most important, DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). The Core has simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is described at RTL level allowing target use in FPGA or ASIC technologies.

More information: http://dcd.pl/ipcore/131/dcan/

DMAC-RMII – the network functionality in design
DMAC-RMII is our newest hardware implementation of a media access control protocol, defined by the IEEE standard. The DMAC-RMII, in cooperation with an external PHY device, enables network functionality in design. This IP Core supports 10BASE-T and 100BASE-TX/FX IEEE 802.3-2002 compliant RMII PHYs.

The DMAC-RMII Core is able to work with the most popular processors available on the market, either 8., 16. and 32 bit data bus, with little or big endian byte order format. Moreover, it provides static configuration of PHY IC, conforming to the IEEE 802.3-2002 standard.  – We’ve always wanted to design the most “user friendly” solutions, that’s why our DMAC-RMII is also technology independent and thus can be implemented in variety of process technologies. – says Jacek Hanke, CEO, DCD-SEMI.  As the Core has been developed for reuse in ASIC and FPGA projects, it’s been implemented in several commercial products already. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.
When the configurability is just one part of the elusive puzzle, the compatibility issues become crucial. That’s why the DMAC-RMII IP Core supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant RMII PHYs. As it’s been stated above, Polish IP Core has a Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers, which ensures maximum compatibility with a great variety of external CPUs or standard bus controllers. – As the host interface can be configured to work with 8., 16. or 32-bit data bus lengths with big or little endian order format – explains Hanke – the DMAC-RMII is compatible with most modern virtual component interfaces. In addition, AMBA, OCP, OPB and other optional standard interfaces are available, which makes the Core a flexible solution to be utilized in a variety of interface applications, including network devices (eg NICs-Network Interface Cards, routers, switching hubs etc.), embedded microprocessor boards, communication systems and other Systems On Chip (SoC) applications.

DRPIC166X MCU, low-cost mixed with high performance

The good old fashioned PIC microcontrollers are finding their way into new applications like smartphones, gaming peripherals, audio devices and embedded solutions for eg innovative medical devices. Moreover, because the DRPIC166X has upward compatible architecture, it preserves investment in code development. And if it’s not enough, let’s just mention that DCD’s IP Core offers 1.3GHz virtual clock frequency and consumes just 37uW/MHz. 

The DRPIC166X is a low-cost high performance 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip), dual ported memory. To fulfill modern electronics requirements, our Core has been designed with a special concern about lowest possible power consumption. It consumes just 37 uW/MHz in 0.18u technology. But power consumption means nothing without reasonable performance. DRPIC166X is the pipelined Harvard RISC architecture, being 4 times faster, compared to original implementation. – PIC family is popular among many engineers due to low cost, wide availability, large user base and extensive collection of application notes – says Jacek Hanke, DCD’s CEO – that’s why we have not only reduced the power consumption, but also increased the performance, DRPIC166X offers 1.3 GHz virtual clock frequency in a 0.18u technological process (800 MHz virtual clock frequency in a 0.35u technology).
The DRPIC166X soft core is software-compatible with the industry standard PIC 16XXX microcontrollers. DCD’s IP Core implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses.
The same, it’s 4 times faster compared to the standard architecture. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage is that the instruction fetch and memory transfers can be overlapped, by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory – explains Hanke. Most instructions are executed within 1 system clock period, except the instructions which directly operate on PC (GOTO, CALL, RETURN) program counter. The pipeline is being cleared and subsequently refilled at additional one clock cycle.
The DRPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices, telecom processors or consumer electronics. Built-in power save mode, makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC166X is delivered with fully automated testbench, complete set of tests and DoCDTM on-chip hardware debugger,  allowing easy package validation, at each stage of SoC design flow.

More information about DRPIC166X: /ipcore/82/drpic166x/

More information about PIC DoCDTM: /page/155/pic-docd/

DQSPI – quad performance SPI

Serial Peripheral Interface – Master/Slave with not only single and dual but most of all quad SPI Bus support, is the newest IP Core introduced by DCD-SEMI. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. IP Core supports all 8, 16, 32 bit processors and has been designed to offer the fastest available operations for any serial memory.

The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device with data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. This quad SPI has been designed to offer the fastest available operations for any serial memory. Moreover the DQSPI has been design to operate with every 8, 16 or 32 bit processor available on the market.
The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. – In the Single SPI mode data is simultaneously transmitted and received – says Jacek Hanke, CEO in DCD-SEMI – in DUAL and QUAD SPI modes – data is shifted in or out on respectively two or four data lines at once.
Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support interprocessor communications.
A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple‐master mode‐fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.

DLIN, Local Interconnect Network IP Core [not only] for automotive

The DLIN is the newest Local Interconnect Network IP Core developed by DCD-SEMI. Our solution is fully compatible with the LIN 1.3, 2.1 and the newest version 2.2 Revision A, released by the LIN Consortium. The core is described at RTL level, empowering the target use in both, FPGA and ASIC tech nologies.

The DLIN, DCD’s IP Core for Local Interconnect Network, is an ideal solution most of all for automotive designs. As technologies and facilities implemented in a car grow every year, the need for a cheap serial network has arisen. That’s why LIN seems to be the most suitable solution to integrate intelligent sensor devices or actuators in today’s cars. Contrary to the CAN, it enables cost competitive serial communication, building the same an extended vehicle’s electrical network, which… will be used as CAN’s sub-network.  – Our DLIN controller supports transmission speed between 1 and 20kb/s – says Jacek Hanke, CEO in DCD-SEMI – that allows to transmit and receive LIN messages compatible to LIN 1.3, LIN 2.1 and also the newest LIN 2.2 rev A.
Compared to the CAN, LIN is slower, but thanks to its simplicity, it is much more cost effective. That’s why the DLIN is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. DCD’s IP Core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or as a slave LIN node, depending on a working mode determined by the microprocessor/microcontroller. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). DCD’s IP Core includes also a programmable timer, which allows to detect timeout and synchronization error. The Core is described at RTL level, empowering the target use in FPGA and ASIC technologies.

More information & data sheet: /ipcore/132/dlin/
DLIN presentation:   http://youtu.be/H72w8laPW5k

The DuART, tiny UART IP Core.

DμART, the newest IP Core mastered by DCD-SEMI, is one of the tiniest UART IP Cores available on the market. Small is beautiful, that’s why DCD’s tiny works not only in UART mode, but also implements separate BAUD clock line, false start bit detection, status report and internal diagnostic capabilities.

The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It can perform both, serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the CPU. The CPU itself can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions, like overrun or framing.
The DμART includes also a programmable baud rate generator – says Jacek Hanke, CEO at DCD-SEMI –  which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock, for driving the internal transmitter logic. Provisions are also included to use this 16 × clock, to drive the receiver logic. The newest UART Core from DCD-SEMI has been also equipped with a processor-interrupt system. Thanks to it, the interrupts can be programmed according to the user’s requirements, minimizing the computing required to handle the communications link.
The DμART core is perfect for applications, where the UART and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. DCD’s solution is also suitable for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices as well.

More information & data sheet: http://dcd.pl/ipcore/690/duart/

D68HC11 – HC11 legacy with all peripherals on board

The D68HC11 is fully software compatible with Motorola’s HC11. DCD’s IP Core offers legacy architecture cycle compatible with original microcontrollers, like 68HC11E, 68HC11A, 68HC11D, 68HC11F1, MC68HC11K0 MC68HC(L)11K1, MC68HC(L)11K4, MC68HC11KS2, MC68HC711K4, MC68HC711KS2, MC68HC11KW1. The D68HC11 can be used as direct replacement, pin-to-pin compatible with the original HC11 MCU.

Based on IP Core architecture improvement experience since 1999, DCD-SEMI has in-troduced two options for the well-known D68HC11:

1. Standard – with preconfigured MCU, where configuration is identical to the original HC11

2. Optimized – an individual configuration with extra peripherals and additional custom blocks, required by the
application [There’s no need to waste time and money for unused features and wasted silicon]

What does it mean in real life/real design?  DCD’s D68HC11 IP Core family is based on 3 major options: E, F, K – explains Jacek Hanke, CEO at DCD-SEMI – they are devoted to the specific original MCU, but in contrast to it – every single one of them adds an extra value to the design, which means, it already has integrated on-chip major peripheral functions. There are asynchronous serial communication interface (SCI) and separate synchronous serial peripheral interface (SPI) included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Moreover, there’s a self-monitoring, on-chip circuitry included, which protects D68HC11E against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides non-maskable interrupt, if the illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available, to conserve additional power. These modes make the D68HC11 IP Cores especially attractive for automotive and battery-driven applications – adds Hanke.
The D68HC11 IP Core, can be also equipped with the ADC Controller. This allows to use an external ADC controller with standard ADC software. This extra design feature added in DCD’s design makes external ADC’s visible in the same way, as internal ADC’s in the original 68HC11E Microcontrollers.
And last but not least, to make the D68HC11 even more adjustable, it’s been equipped with a built-in, real-time, on-chip hardware debugger, allowing easy software debugging and validation. Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
DCD’s IP Core comprises also fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.

More information about D68HC11: /ipcores/59/  & http://www.youtube.com/watch?v=1dtE1jHBO54
More details about DCD on Chip Debugger: /page/156/d68xx-docd/

The D26C92 UART IP Core offers more

The D2692 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681. But on the contrary to it, DCD’s IP Core offers additional features and deeper FIFOs, like 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.

The D2692 Dual Universal Asynchronous Receiver/Transmitter is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in just one single package. DCD’s IP Core interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. – Additionally, each receiver and transmitter can select its operating speed – says Jacek Hanke, DCD’s CEO – as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The opportunity to program independently the operating speed of the receiver and transmitter, denotes the UART particularly attractive for dual-speed channel applications like eg clustered terminal systems.
Every receiver is being equipped with FIFO to minimize the potential of receiver over-run and to re-duce interrupt overhead in interrupt driven systems. Moreover, the D2692 UART IP Core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. To make this design even more functional, there’ve been added multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.

Detailed information: http://dcd.pl/ipcore/785/d2692/

DSPI_FIFO – SPI master slave enhanced with detectors

The DSPI_FIFO is a fully configurable SPI master/slave device, which allows to configure polarity and phase of a serial clock signal SCK. DCD’s core enables microcontroller to communicate with serial peripheral de-vices, but also to communicate with an interprocessor in a multi-master system. It supports all the features of SPI and transmission/reception FIFOs, to significantly reduce the CPU time.

The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, even from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows to select clock polarity and choose two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. – A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines – explains Jacek Hanke, CEO at DCD-SEMI – so the data is simultaneously transmitted and received.
The DSPI_FIFO automatically drives selected by the SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communication.
A write collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DCD’s IP Core is technology independent and silicon proven design. It is fully customizable, which means it is delivered in the exact configuration of customer’s requirements. – There is no need to pay extra for not used features and wasted silicon – ends Hanke. The DSPI_FIFO includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Detailed information: http://dcd.pl/ipcore/125/dspi-fifo/

Programmable Interrupt Controller D8259 from DCD-SEMI

DCD-SEMI, IP Core provider and the System on Chip design house from Poland introduced in its offer the D8259. DCD’s Programmable Interrupt Controller is fully compatible with the 82C59A device. As all other cores design by Polish company, the D8259 is tech-nology independent, so it can be implemented both in ASIC and FPGA.

The D8259 is a soft Core of Programmable Interrupt Controller, which is fully compatible with the 82C59A device. DCD’s IP core can manage up to 8-vectored priority interrupts for the processor. – But that’s not all, cause you can also program it to cascade and gain up to 64 vectored interrupts  – adds Jacek Hanke, DCD’s CEO. And if it still seems to be not enough, one can always get more than 64 vectored interrupts, by programming the D8259 to the Poll Command Mode.
The D8259 Package includes fully automated testbench. Thanks to complete set of tests, one can easily validate the whole package at each stage of SoC design flow. Same as all other DCD’s IP Cores, this one’s got also a technology independent design, that can be implemented in a variety of process technologies.
The D8259 can operate in all 82C59A modes and it supports all 82C59A features:

More information about D8259 IP Core: http://dcd.pl/ipcore/134/d8259/

DCD’s HDLC/SDLC controller aims telecommunication

DCD-SEMI has introduced our latest soft IP Core, the DHDLC. It’s been designed to control HDLC/SDLC transmission frame and optimized for great variety of 8, 16 and 32-bit MCUs. Same as all other DCD’s IP Cores, the DHDLC is a technology independent design, therefore can be implemented in both, ASIC and FPGA.

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, no matter if it’s 8-, 16- or 32-bit microcontroller. The greatest advantage of this IP Core is the possibility to save MCU time wasted for handling HDLC/SDLC features, like bit stuffing, address recognition and CRC computation. To enable even more productivity, the DHDLC has an implemented FIFO buffer, for both receiver and transmitter. – We’ve designed the DHDLC IP Core, because… our customers asked us to do it so many times – explains Jacek Hanke, DCD’s CEO. Configurable core parameters and adjustable CPU interface are a must be in this project.
The DHDLC IP Core is fully synchronous with one clock domain design. All parameters are configurable by CPU, but there is also an another option. One can set all the parameters by modification constants in a source file. Thanks to it, there’s no need to waste silicon resources for unused features and constant settings.

DHDLC’s Key Features:

More information about the DHDLC IP Core: http://dcd.pl/ipcore/670/dhdlc/

EEPROM IP Core with configurable SPI parameters

DCD-SEMI, IP Core and System on Chip design house from Poland introduced its latest solution – DEEPROM. It performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Moreover, DCD’s IP Core DEEPROM implements configurable SPI parameters like serial clock prescaler, SPI mode, CS hold/setup.

DCD-SEMI, celebrating in 2014 its 15th anniversary introduced newest IP Core which targets DRAM designs. The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. – Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory – says Jacek Hanke, DCD’s CEO. The controller automatically sends all control instructions and read /write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it’s visible and controlled as parallel SRAM with long access time. – DEEPROM’s big advantage is that the core has been designed to operate with popular 25XXX SPI Serial EEPROMs from Atmel, Microchip – adds Hanke.
When all other factors are sustained, memory controller is becoming crucial. That’s why DCD’s IP Core has been developed to ensure the most accurate data flow. It was designed in accordance with JEDEC specification and all the other industry standards, which summarized together make the DEEPROM very small, efficient, with no internal tri-state buffers and signals IP Core.

More information: http://dcd.pl/ipcore/146/deeprom/

Watch the DEEPROM presentation on You Tube: http://youtu.be/lHbSfQAerlM

DEEPROM’s Key Features:

100 million instructions for (good old?) M68HC08
DCD’s DF6808 IP Core is binary-compatible with the industry standard Motorola 68HC08 8-bit microcontroller, but thanks to highly sophisticated on-chip peripheral capabilities, it performs 45-100 million instructions per second. FAST architecture implemented in DF6808 enable this mcu to run at least 3 times faster than the original solution.

DCD-SEMI, celebrating its 15th anniversary in 2014, enhanced its portfolio with a new architecture. DF6808, even in standard configuration, offers integrated on-chip major peripheral functions. But, as the company’s CEO Jacek Hanke has stated, it’s just the beginning: “The DF6808 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI) and the Synchronous Serial Peripheral Interface (SPI)”. To enable even more functionality in design,  the main 16-bit, free-running timer system, has two input capture lines and two output-compare lines.
The DF6808 has been equipped with proprietary safety functions, which efficiently hasten the design process. To protect against system errors, self-monitoring circuitry has been included on-chip. The Computer Operating Properly (COP) watchdog system, protects against software failures. And an illegal opcode detection circuit provides a non-maskable interrupt, once the illegal opcode occurs.
Two software-controlled power-saving modes – WAIT and STOP are available to conserve additional power. These modes make the DF6808 IP Core especially attractive for automotive and battery-driven applications.
The DF6808 is fully customizable, which means it’s been delivered in the exact configuration, to meet target design requirements. There is no need to pay extra for unused features and wasted silicon. DCD’s IP Core includes fully automated test bench with complete set of tests. They allow easy package validation at each stage of SoC design flow.
And last but not least, the DF6808 has a built-in support for DCD Hardware Debug System called DoCD. It’s a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCD enables non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of micro-controller, including all registers, SFRs, user defined peripherals, data and program memories.

 

More information: http://dcd.pl/ipcore/113/df6808/

 

DF6808’s Key Features:

D16950 – ask for more from UART
DCD, celebrating our 15th anniversary, has released the D16950, which is an IP Core of a Uni-versal Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes.

DCD’s UART IP Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM. And for those who need more, the D16950 enables also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). – The D16950 includes a programmable baud rate generator, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic – explains Jacek Hanke, DCD’s CEO.  Provisions are also included to use this n × clock to drive the receiver logic.
The D16950 UART IP Core is equipped with a complete MODEM-control capability and a processor-interrupt system. – Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link – adds Hanke. The D16950 core includes all other UARTs (16450, 16550, 16650 and 16750) features and additional functions. Saying this, one can mention the ICR registers, which give additional capabilities of UART work configuration. The data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register enables a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers, with any value set from 1 to 127.
DCD’s IP Core implements also auto flow control feature, which can significantly reduce software overload and automatically increase the system efficiency, by controlling serial data flow through the RTS output and the CTS input signals.
The D16950 is perfect for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it’s also a proprietary solution for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal inter-face, the D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
DCD’s IP Core includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. The D16950 is also a technology independent design, that can be implemented in a variety of process technologies.

More information: http://dcd.pl/ipcore/130/d16950/

 

D16950 Key Features:

A rethought PIC IP Core – the DRPIC1655X
DCD-SEMI, IP Core provider and System-on-Chip design house, celebrating in 2014 15th Anniversary, presents the DRPIC1655X IP Core, which is compatible with the industry standard PIC 16XXX, but…  ensures 4 times faster architecture and 1 system clock instruction execution time. Thanks to its price and software simplicity, engineers can minimize the software development costs and enable easy portability across low to high-end platform.

The DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast, dual ported memory. It’s been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the PIC IP cores market. – Especially now, when we see more demand from IoT projects – explains Jacek Hanke, DCD’s CEO – efficient solutions like DRPIC1655X are the right answer, cause one can find them for less than $1 in 10K quantities. But of course FPGA netlist is also available.
The DRPIC1655X Microcontroller perfectly fits in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC1655X IP core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memoryallow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory.
The DRPIC1655X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. – This situation requires the pipeline to be cleared and subsequently refilled – adds Hanke – This operation takes additional one clock cycle.
Last but not least, the DRPIC165X is delivered with fully automated testbench, complete set of tests and DoCD on-chip hardware debugger,  which allow easy package validation, at each stage of SoC design flow.
Unlike other on-chip debuggers, DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

More information: http://dcd.pl/ipcore/81/drpic1655x/

 

CPU Key Features:

D68HC11K with applications notes, development board & tools
DCD-SEMI, celebrating our 15th anniversary this year, has introduced the D68HC11K, which is a synthesizable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard. It can be used as a direct replacement for the microcontrollers like: MC68HC11K0, MC68HC11K1, MC68HC11K4, MC68HC711K4, MC68HC11KS2 and MC68HC711KS2.

In a standard configuration, the core has an integrated on-chip major peripheral functions. An asynchronous serial communication interface (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. – This and additional modes make the D68HC11K IP Core especially attractive for automotive and battery-driven applications – says Jacek Hanke, DCD’s CEO. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Self-monitoring, on-chip circuitry is included, to protect D68HC11K against system errors. To enable optimal functionality in design, DCD’s IP Core implements eg:

The D68HC11K Microcontroller Core can be equipped with the ADC Controller, which allows the us-age of external ADC Controller with standard ADC software. This ADC Controller makes external ADC’s visible in exact the same way as internal ADC’s in original 68HC11K Microcontrollers.
DCD’s IP Core is fully customizable – it is delivered in the exact configuration, to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
And last but not least, to allow easy software debugging and validation, the D68HC11K has a built-in support for DoCD – a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
More information: http://dcd.pl/ipcore/88/d68hc11k/

DF6811E – 4 times faster architecture for HC11
DCD-SEMI, celebrating our 15th anniversary in 2014, introduced the DF6811E IP Core. It aims at IoT sensors and beacons, but thanks to its binary compatibility with the Motorola’s 68HC11, it can be implemented in barcode readers, hotel card key writers, robotics, and various embedded systems.

 

The DF6811E is a redefined 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. Even though it is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller, DCD’s IP Core has an improved FAST architecture. Thanks to it, it is approximately 4 times faster when compared to the original implementation. In the standard configuration, the core has integrated on-chip, major peripheral functions in one of below configurations:
+ 68HC11A
+ 68HC11D
+ 68HC11E
The DF6811E implements two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. – Our Core offers also enhanced security by implementing self-monitoring circuitry included on-chip and the Computer Operating Properly (COP) watchdog system to protect against software failures – explains Jacek Hanke, DCD’s CEO. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP, are available to conserve additional power.
The DF6811E Microcontroller Core can be equipped with the ADC Controller, which allows using an external ADC Controller with standard ADC software. The ADC Controller makes external ADC’s visible as internal ADCs in original 68HC11E Microcontrollers. The DF6811E has built-in real time, on-chip hardware  debugger – DoCDTM, which enable easy software debugging and validation.
The DF6811E is a silicon proven and fully customizable solution. DCD delivers it in the exact configu-ration, which allows the licensee to save his time and money (there’s no need to pay extra, for not used features and wasted silicon). The package includes also fully automated test bench with complete set of tests to validate it at each stage of SoC design flow.